1. Field of the Invention
The present invention relates to a wideband amplifier for use in a switched capacitor circuit in the field of an analog integrated circuit technology.
2. Description of the Related Art
FIG. 1A is a circuit diagram showing a sample and hold circuit of such a pipeline ADC (Analog to Digital Converter) as described in a literature by Yong-In Park, S. Karthikeyan, Frank Tsay and Eduardo Barlolome, entitled “A 10b 100Msample/s CMOS Pipelined ADC with 1.8V Power Supply,” IEEE International Solid-State Circuits Conference, pp. 130-131, 2001. FIG. 1B is a circuit diagram showing an operational amplifier for use in this sample and hold circuit.
As shown in FIG. 1A, this sample and hold circuit, which has an architecture generally referred to as the “Flip Around SHA,” is provided with nodes NIp and NIm to which differential input signals VIp and VIm are supplied via switches Slp and Slm, respectively. The nodes NIp and NIm are connected to the plus(+) input terminal and minus(−) input terminal of an operational amplifier 10 via capacitors CSp and CSm, respectively, as well as to the minus(−) output terminal and plus(+) output terminal of the operational amplifier 10 via switches S2p and S2m, respectively.
The operational amplifier 10 receives a reference voltage Vcm at the plus input terminal and the minus input terminal via switches S3p and S3m, respectively. On the other hand, the operational amplifier 10 is connected to a ground potential GND at the plus output terminal and the minus output terminal via load capacitors CLp and CLm, respectively, and short-circuited therebetween by a switch S4.
Between the plus and minus input terminals of the operational amplifier 10 and the ground potential GND, there are formed input capacitance Cip and Cim, which are not connected as actual components but have detrimental effects on the operation of the operational amplifier 10 at high frequencies.
On the other hand, as shown in FIG. 1B, the operational amplifier 10 is formed of a typical two-stage differential amplifier with an input stage and an output stage.
The input stage 10-1 has N-channel MOS transistors 11a and 11b to which a differential input signal is supplied (hereinafter the MOS transistor is simply referred to as “MOST” and the N-channel MOS transistor as “NMOST”). The gates of the NMOSTs 11a and 11b serve as the plus input terminal and the minus input terminal of the operational amplifier 10, respectively. The sources of the NMOSTs 11a and 11b define a common connection and are connected to a potential VSS via a constant-current supply 12 and an NMOST 13, which are connected in parallel to each other.
The drains of the NMOSTs 11a and 11b are connected to nodes Na and Nb via NMOSTs 14a and 14b, respectively. The node Na is connected to a potential VDD via P-channel MOS (hereinafter referred to as “PMOST”) 15a and 16a, which are connected in series to each other, while the node Nb is connected to the potential VDD via PMOSTs 15b and 16b, which are connected in series to each other.
The output stage 10-2 includes NMOSTs 17a and 17b having the gates connected to the nodes Na and Nb, respectively. The sources of the NMOSTs 17a and 17b are commonly connected to the potential VSS via a constant-current supply 18 and an NMOST 19, which are connected in parallel to each other. The drains of the NMOSTs 17a and 17b are connected to the potential VDD via PMOSTs 20a and 20b, respectively.
The drains of the NMOSTs 17a and 17b serve as the plus output terminal and the minus output terminal of the operational amplifier 10, respectively. Between the drain of the NMOST 17a and the node Na, there are a zero correction resistor 21a and a Miller capacitor (a phase compensation capacitor) 22a connected in series to each other. Between the drain of the NMOST 17b and the node Nb, a similar resistor 21b and a Miller capacitor (a phase compensation capacitor) 22b are connected in series to each other.
The gates of PMOSTs 16a, 16b, 20a and 20b are connected to a bias potential VB1, the gates of the PMOSTs 15a and 15b to a bias potential VB2, and the gates of the NMOSTs 14a and 14b to a bias potential VB3. Furthermore, the gates of the NMOSTs 13 and 19 are connected to bias potentials VB4 and VB5, respectively.
FIG. 2 is a view illustrating an equivalent circuit of the sample and hold circuit of FIG. 1A for a small high-frequency signal during a hold operation.
As shown in FIG. 2, during a hold operation, the input stage 10-1 and the output stage 10-2 of the operational amplifier 10 are connected in series, and the load capacitors CLp and CLm (with capacitance Cl) are connected between the output of the output stage 10-2 and the ground potential GND. The input and output of the output stage 10-2 are also connected to each other via the Miller capacitors 22a and 22b (with capacitance Cm). Additionally, the output of the output stage 10-2 and the input of the input stage 10-1 are connected to each other via the capacitors CSp and CSm (with capacitance Cs). Moreover, there is formed input capacitance Ci1 between the input of the input stage 10-1 and the ground potential GND, while input capacitance Ci2 is formed between the input of the output stage 10-2 and the ground potential GND.
In the above equivalent circuit, a closed-loop bandwidth BWcl indicative of an operation bandwidth is expressed as in the following equation (1):                                                         BWcl              =                            ⁢                              BWop                ×                β                                                                                                        =                                ⁢                                                      {                                                                  gm1                                                  Ci2                          +                                                      Cm                            ⁡                                                          (                                                              1                                +                                gm2                                                            )                                                                                                                          ×                                              gm2                                                  Cl                          +                                                                                    Cs                              ×                              Ci1                                                                                      Ci1                              +                              Cs                                                                                                                                            }                                    ×                                      Cs                                          Ci1                      +                      Cs                                                                                  ,                                                          (        1        )            
where BWop is the bandwidth of the operational amplifier 10, β is the feedback factor, and gm1 and gm2 are the mutual conductance of the input stage 10-1 and the output stage 10-2, respectively.
In the above equation (1), since Cm(1+gm2)>>Ci2 and gm2>>1, the equation (1) can be approximately given by the following equation (2):                     BWcl        =                              gm1            Cm                    ×                                    Cs                                                Ci1                  ⁡                                      (                                          Cl                      +                      Cs                                        )                                                  +                                  Cl                  ×                  Cs                                                      .                                              (        2        )            
The mutual conductance gm1 and the input capacitance Ci1 of the input stage 10-1 can be expressed as in the following equations (3) and (4):gm1=√{square root over (2μ×Cox×Id×W/L)},  (3)Ci1=Cox×W×L,  (4)
where W is the gate width of the NMOSTs 11a and 11b, L is the gate length, μ is the electron mobility, Cox is the per-unit capacitance of the gate oxide film and Id is the drain current.
Substituting the equations (3) and (4) into the equation (2), the closed-loop bandwidth BWcl is expressed as in the following equation (5):                                                         BWcl              =                            ⁢                                                Cs                  Cm                                ×                                                                            2                      ⁢                      μ                      ×                      Cox                      ×                      Id                      ×                                              W                        /                        L                                                                                                                        Cox                      ×                      L                      ×                                              W                        ⁡                                                  (                                                      Cl                            +                            Cs                                                    )                                                                                      +                                          Cl                      ×                      Cs                                                                                                                                              =                            ⁢                                                Cs                  Cm                                ×                                                                                                    2                        ⁢                        μ                        ×                        Cox                        ×                                                  Id                          /                          L                                                                                                                                    Cox                        ×                        L                        ×                                                  W                                                ⁢                                                  (                                                      Cl                            +                            Cs                                                    )                                                                    +                                                                        Cl                          ×                          Cs                                                                          W                                                                                                      .                                                                                        (        5        )            
The above equation (5) shows that the operation bandwidth of the sample and hold circuit employing a two-stage operational amplifier for performing phase compensation with Miller capacitance is determined by the dimensions of the gate length L and the gate width W of an input MOST at the input stage of the operational amplifier. Therefore, to maximize the operation bandwidth, the gate length L should be set at the minimum gate length Lmin or the lower limit available to the manufacturing process, while the gate width W should be set at an optimal dimension that can be obtained from the equation (5), i.e., the optimum gate width Wopt.
The optimum gate width Wopt takes the value as shown by the following equation (6), which is derived from the equation (5) by differentiating its denominator with respect to W to determine the value of W by which the result of the differentiation gives zero.                     Wopt        =                                            Cl              ×              Cs                                      Cox              ×                              L                ⁡                                  (                                      Cl                    +                    Cs                                    )                                                              .                                    (        6        )            
Using the minimum gate length Lmin and the optimum gate width Wopt, the maximum operation bandwidth BWmax of the sample and hold circuit shown in FIG. 1A is expressed as in the following equation (7):                               BW          ⁢                                           ⁢          max                =                              Cs            Cm                    ×                                                                      2                  ⁢                  μ                  ×                  Cox                  ×                  Id                  ×                                      Wopt                    /                    L                                    ⁢                                                                           ⁢                  min                                                                              Cox                  ×                  Wopt                  ×                  L                  ⁢                                                                           ⁢                                      min                    ⁡                                          (                                              Cl                        +                        Cs                                            )                                                                      +                                  Cl                  ×                  Cs                                                      .                                              (        7        )            
However, the prior art operational amplifier has the following problems.
That is, as shown in the equation (7), the maximum operation bandwidth BWmax of the sample and hold circuit incorporating this operational amplifier is determined by the electron mobility μ, the per-unit capacitance (of a gate oxide film) Cox, and the minimum gate length Lmin. However, since the manufacturing process employed determines these values, there has been a problem that the manufacturing process imposes limitations on the maximum operation bandwidth BWmax, which is also reduced by the value of the phase compensation capacitance Cm.